Receiver of multiplexed binary offset carrier (MBOC) modulated signals

ABSTRACT

A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which arc different to the code rate, the receiver comprising processing means arranged to: generate a first estimate of delay based on the code modulation only; generate a second estimate of delay based on the first component of the sub-carrier modulation only; and generate a third estimate of delay based on the second component of the sub-carrier modulation only; and determine a further delay estimate from the first second and third delay estimates.

FIELD OF THE INVENTION

The present invention relates to the reception of Multiplexed BinaryOffset Carrier (MBOC) modulated signals and similar such signals. Oneparticular application of the invention is the reception of MBOCmodulated navigation signals in a Global Navigation Satellite System(GNSS).

BACKGROUND TO THE INVENTION

In a GNSS, a receiver estimates delays τ in the navigation signalsreceived from different satellites and uses this information, combinedwith information on the position of the satellites, to estimate itsposition. The more accurate the estimation of the delays τ, the moreaccurately the receiver can estimate its position.

The United States led Global Positioning System (GPS) is presently theGNSS in most common use. Navigation signals transmitted by GPSsatellites are modulated using a Phase Shift Keying (PSK) modulation ofa code onto a carrier signal having a designated carrier frequency. Themodulation involves altering the phase of the carrier signal by fixedamounts (0 or π) at a code rate f_(C), each symbol of the code havingduration T_(C)=1/f_(C) and the code being repeated with time periodT_(G). A navigation signal received at a receiver from a satellite cantherefore be represented by an equivalent bi-modal amplitude modulationfunction α(t−τ)ε(−1,+1) with period T_(G), as shown in FIG. 1.

The receiver estimates the delay τ by comparing the received signal to alocally generated reference signal. The reference signal consists of anin-phase and quadrature-phase (I and Q) carrier modulated with the samecode as the input signal. The reference modulation can be representedmathematically as a(t−{circumflex over (τ)}) where {circumflex over (τ)}is a trial delay. The comparison typically consists in multiplying thereceived signal by the I and Q reference to yield a demodulated signal.The demodulated signal is then integrated over a given time, usually thesame as the period T_(G) of the code, to output a value known as acorrelation. The correlation depends on the difference between the trialdelay {circumflex over (τ)} of the reference signal and the true delay τof the received signal and can be expressed as a correlation functionΛ({circumflex over (τ)}−τ). As shown in FIG. 2, this correlationfunction for a PSK modulated signal is triangular and peaks when thetrial delay {circumflex over (τ)} matches the true delay τ The width ofthe correlation function is twice the symbol duration T_(C), i.e.2T_(C).

Calculating the entire correlation function Λ({circumflex over (τ)}−τ)over all {circumflex over (τ)} and analysing it to determine its peakand hence identify the delay τ of the received signal is acomputationally time-consuming task. Most conventional GPS receiverstherefore compute just three sampled correlations simultaneously, usingthree reference signals offset in time from one another. The threecorrelations are usually referred to as gate values of Early (E), Prompt(P) and Late (L) gates. The E and L gates are offset from one another bya time separation T_(DC), so that they can be considered to have trialdelays

$\hat{\tau} - {\frac{T_{DC}}{2}\mspace{14mu}{and}\mspace{14mu}\hat{\tau}} + \frac{T_{DC}}{2}$respectively. The P gate can then be considered to have trial delay{circumflex over (τ)} half way between these trial delays of the E and Lgates. So, as illustrated in FIG. 2, when the E and L gate values areequal, the P gate value yields the peak value of the correlationfunction Λ({circumflex over (τ)}−τ) and the trial delay {circumflex over(τ)} is equal to the true delay τ.

An iterative algorithm can be used to arrive at this state. When thetrial delay {circumflex over (τ)} is not equal to the true delay, the Pgate will be offset from the peak of the correlation function Λ( ) andthere will be a difference in the values of the E and L gates. So, anerror signal proportional to the difference between the trial delay{circumflex over (τ)} and the true delay τ can be generated bysubtracting the E gate value from the L gate value. This can be used toiteratively adjust the trial delay {circumflex over (τ)} toward the truedelay τ. A best estimate of the true delay is then deemed to be thevalue of the trial delay (of the P gate) when the E gate value is equalto the L gate value (as shown in FIG. 2).

It is presently intended to improve the American GPS by adding newnavigation signals to the system. The independent European Galileosystem will use similar new navigation signals in both the same and newfrequency bands. While some of the new navigation signals will continueto use PSK modulation, most of them will be modulated using the newBinary Offset Carrier (BOC) modulation which is described first. Animportant sub-set of BOC is called Multiplexed binary offset carrier andis described next.

BOC Modulation.

BOC modulation is like PSK in that it involves modulating a code onto acarrier. The code is similar to that used in PSK modulation, and thecode in the received signal can again be represented by an equivalentbi-modal amplitude modulation function a(t−τ) having code rate f_(C),symbol duration T_(C) and periodicity T_(G). However, BOC involvesfurther modulating the signal by a sub-carrier, which can be representedby a sub-carrier modulation function s(t−τ) having sub-carrier ratef_(s) and sub-symbol duration equivalent to a half-cycleT_(S)=1/(2f_(S)). As seen in FIG. 3, the sub-carrier modulation functions(t−τ) is a simple periodic square waveform. The sub-carrier rate f_(s)is an integer multiple, or an integer-and-a-half multiple of the coderate f_(C). The standard notation for BOC modulation reads BOC(f_(s),f_(C)). This figure shows what can be called ‘sine-BOC’ where the subcarrier has 0 deg phase shift relative to the code zero crossings. Alsothere is ‘cosine-BOC’ where the sub-carrier is phase shifted 90 degrelative to the code zero-crossings (not shown).

When a received BOC signal is correlated using a matching locallygenerated BOC reference signal the resulting correlation function

({circumflex over (τ)}−τ) has multiple peaks. For example, referring toFIG. 4 a, this correlation function of a sine-BOC signal modulated usingBOC(2f, f) has three positive peaks and four negative peaks. The centralpositive peak corresponds to a match of the true delay τ of the receivedsignal with the trial delay of the reference signal. The other,secondary peaks are separated at intervals of the sub-symbol durationT_(s). Importantly, the envelope (dashed line) of this correlationfunction

({circumflex over (τ)}−τ) is the same as the correlation functionΛ({circumflex over (τ)}−τ) of a PSK modulated signal having the samecode rate f_(C).

Because the central peak of the BOC correlation function

({circumflex over (τ)}−τ) has steeper sides than the peak of theequivalent PSK correlation function Λ({circumflex over (τ)}−τ), BOCmodulation has the potential to allow more accurate delay estimation.Specifically, when the E and L gates are located on either side of thecentral peak then the error signal generated from the difference betweenthe L gate value and the E gate value can steer the P gate to the top ofthe central peak and hence the trial delay {circumflex over (τ)} to thetrue delay τ, as illustrated in the top part of FIG. 4 a. There ishowever an inherent ambiguity in the delay estimate for a BOC signalprovided by the conventional delay estimation technique, as describedabove. When the E and L gates reside on either side of one of thesecondary peaks, the error signal will steer the P gate to the secondarypeak (which can be negative). In that situation, the error signal willbe zero, just as it is when the P gate is at the top of the centralpeak, and the iteration will have converged to a value of the trialdelay {circumflex over (τ)} that does not correspond to the true delayτ. This is known as ‘false lock’ or ‘slip’, or ‘false node tracking’.

A number of techniques have been proposed for overcoming this problemwith pure BOC. One such technique, commonly referred to as ‘bumpjumping’, is described in the paper “Tracking Algorithm for GPS OffsetCarrier Signals”, P. Fine et al, Proceedings of ION 1999 NationalTechnical Meeting, January 1999. This technique takes advantage of theknowledge that adjacent peaks of the BOC correlation function

({circumflex over (τ)}−τ) are separated from one another by the knownsub-carrier symbol duration T_(s). Specifically, the technique tests forcorrect location of the P gate using a pair of gates, called Very Early(VE) and Very Late (VL) gates, having trial delays {circumflex over(τ)}−T_(S) and {circumflex over (τ)}+T_(S) respectively. These areoffset from the trial delay {circumflex over (τ)} of the P gate by thesub-carrier symbol duration T_(S). So, if the P gate has converged tothe top of one of the peaks, e.g. the receiver is in lock, the VE, P andVL gates are located on three adjacent peaks. At this stage, the VE, Pand VL gate values are compared. If the VE and VL gate amplitudes areless than the P gate amplitude, the P gate is known to lie on thecentral peak and the trial delay {circumflex over (τ)} corresponds tothe true delay. However, if the VE or VL gate amplitude is higher thanthe P gate value, the P gate is on a secondary peak. In this event, thetrial delay {circumflex over (τ)} is incremented by the sub-symbolduration T_(s) in the direction of whichever of the VE and VL gates hasthe higher (modulus) value. This action should cause the P gate to jumpto the next peak toward the central peak. The comparison is thenrepeated to verify that the P gate is on the central peak or to causerepeated incrementing of the trial delay {circumflex over (τ)} until theP gate is located on the central peak.

Bump jumping allows a receiver to fully exploit the potential accuracyof BOC. However, there can be a significant waiting time before thedelay estimate can be relied on. There is an elapsed time required todecide whether there is a false lock or not. This is longer for a lowC/N₀, when the VE, P and VL gate values must also be averaged over asignificant time in order to be sure which of the three tested adjacentpeaks has the highest amplitude. The required time to detect false lockalso increases proportionally with the ratio of the sub-carrier rate tothe code rate f_(S)/f_(C), because the difference of amplitude betweenadjacent peaks relatively decreases. It may also be necessary to correctfalse lock several times over successive secondary peaks before thecentral peak is found, a problem which is exacerbated as the ratio ofthe sub-carrier rate to the code rate f_(S)/f_(C) increases, because thenumber of secondary peaks increases. Overall, the waiting time may rangeupwards to several seconds, which is certainly enough to havepotentially disastrous consequences for a plane landing, ship docking orsuch like. Worse, the receiver does not know that it has been in a falselock state until it actually jumps out of it. The bump jumping systemtherefore is not fail safe.

A further difficulty has now been realised since the launch of the firsttest satellite GIOVE-A transmitting BOC signals in December 2005.Non-linear and linear distortion in the transmitting chain can easilycause appreciable asymmetry in the actual correlation function

({circumflex over (τ)}−τ)—where the corresponding secondary peaks oneither side of the main peak are no longer equal in amplitude. Thisinevitably degrades performance, and in a worst case, the bump-jumpingreceiver simply does not work. Recent practical tests are described in“GIOVE-A in orbit testing results” M. Falcone, M. Lugert, M. Malik, M.Crisic, C. Jackson, E. Rooney, M. Trethey ION GNSS FortWorth Tex.,September 2006.

FIG. 4 b is a simulation of the effect of extreme phase distortion (90deg). It shows that the later (negative) secondary peak has the sameamplitude as the (positive) primary peak. In such a case the VEVLreceiver must fail. For less extreme phase distortion—the unbalancingmust degrade signal to noise performance, simply because it brings theamplitude of one of the secondary peaks closer to the amplitude of theprimary peak.

The paper “Unambiguous Tracker for GPS Binary-Offset-Carrier Signals”,Fante R., ION 59th Annual Meeting/CIGTF 22nd Guidance Test Symposium,23-25 Jun. 2003, Albuquerque, N. Mex., describes another techniqueinvolving multiple sampling (gating) of the correlation function andthen linear combination of these samples to synthesise a monotonicapproximation to the PSK correlation function Λ({circumflex over (τ)}−τ)having no multiple peaks. This solution certainly eliminates falselocks. However, this technique relies on a very complex receiver design.More fundamentally, it fails to realise the potential accuracy conferredby BOC modulation, because the shallower PSK correlation peak is reliedon to resolve the delay estimate. Similarly, the paper “BOC(x, y) signalacquisition techniques and performances”, Martin et al., Proceedings ofION GPS 2003, September 2003, Portland, Oreg., describes a techniquethat exploits the fact that the BOC modulated signal has a mathematicalequivalence to two PSK modulated signals centred on two separate carrierfrequencies; where the higher frequency f_(H) is equal to the carrierfrequency plus the sub-carrier frequency f_(S) while the lower frequencyf_(L) is equal to the carrier frequency minus the sub-carrier frequencyf_(S). With appropriate processing the actual monotonic PSK correlationfunction) Λ({circumflex over (τ)}−τ) can be recovered. But this methodis again complex to implement and more fundamentally fails to realisethe potential accuracy conferred by BOC modulation.

The solution—described in detail in patent application GB0624516.1—is toeliminate the problem by eliminating the correlation

( ). Instead, a two dimensional correlation is tracked independently torealise a dual estimate. An unambiguous lower accuracy estimate derivedfrom the code phase is used to make an integer correction to a higheraccuracy but ambiguous independent estimate based on the sub-carrierphase. The actual receiver may adopt a triple loop, instead of the usualdouble loop, where carrier phase, sub-carrier phase and code phase aretracked independently but interactively.MBOC Modulation.

Multiplexed binary offset carrier (MBOC) has been proposed in animportant modification of BOC. See “MBOC—the new optimized spreadingmodulation recommended for L1 O and GP L1C” published May/June 2006Inside GNSS. The proposal is authored and agreed by internationalexperts G. W. Hein, J-Avial Rodriguez, S Wallner, J. W. Betz, C. J.Hegarty, J. J. Rushanan A. L. Kraay, A. R. Pratt, S. Lenahan, J. Owen,J-L Issler and T. Stansell. When adopted it will add a further layer ofcomplexity to reception of GNSS signals compared to ordinary BOCmodulation, which is in turn more complicated than PSK modulation. Itoffers improved accuracy and better rejection of multi-path.

The basis is to make the sub-carrier modulation a linear superpositionof BOC(1,1) and BOC(6,1). A common agreed code is described asMBOC(6,1,1/11). The notation implies that 1/11 of the total power is theBOC(6,1) component—and 10/11 of the power is the BOC(1,1) component. Thelinear superposition can be done by time domain multiplexing where 1/11of the BOC(1,1) symbols are replaced by BOC(6,1) symbols (same chipwidth T_(C)=1 μs) having same amplitude (TMBOC). The currently favouredalternative is in the frequency domain multiplexing where there iscontinuous modulation with unequal amplitudes of the two components(CBOC). Whichever form is adopted makes no difference to the invention.Current proposals divide power into data channel and pilot channel. Onecurrent proposal assumes a 50-50 division of power and with no BOC(6,1)component in the data channel, putting it all in the pilot channel. Onthat basis then the relative proportions of the two components in thepilot channel is 9/11 of BOC(1,1) and 2/11 of BOC(6,1) for which anexample is shown in FIG. 5. Whatever proportions are finally decidedmakes no difference to the invention.

The difference from BOC is clearly seen in the form of a doubly periodicmodulation with half periods described by two different sub-chip widthsT_(S1) and T_(S2). When recovered in the conventional single estimatereceiver an even more complicated correlation function as in FIG. 6 a isthe result. We shall adopt the notation

( ) for the correlation function. Not only are there two secondary(negative) peaks but there are also multiple tertiary peaks. Incomparison with the ordinary correlation function for BOC(1,1)—shown asdotted—the slope magnitudes either side of the main peak arehigher—which quantifies as an improved accuracy if tracking is correct.But clearly the new modulation offers many more opportunities for falsetracking on the ‘ripples’ in the correlation function—for example as inFIG. 6 b, when the gate width is narrow, as it has to be for potentiallyaccurate tracking. These figures are for ideal shapes with no phasedistortion. As might be expected the new MBOC is more sensitive to phasedistortion than BOC. The synthesised effect of phase distortion is shownin FIG. 6 c (with 50 deg distortion on BOC(6,1,1/11) where it is clearthat the correlation function cannot be tracked because there is asecondary peak equal in amplitude to the primary peak. The complexitiesof equalization will be needed therefore in order to realize anadequately symmetrical function. At the present time MBOC is so new thatno proposals have been published on how to design a receiver to overcomethe problems that this complex modulation will entail.

The present invention overcomes the problem of tracking MBOC. Thesolution is to eliminate the problem by eliminating the correlationfunction

( ). Instead, a three dimensional correlation is tracked independentlyto realise a triple estimate. An unambiguous lower accuracy estimatederived from the code phase is used to make an integer correction to ahigher accuracy but ambiguous independent estimate based on the lowerfrequency sub-carrier phase which in turn is used to make an integercorrection to even higher accuracy but ambiguous independent estimatebased on the higher frequency sub-carrier phase. The actual receiver mayadopt a quadruple loop, instead of the usual double loop, where carrierphase, sub-carrier₂ phase, sub-carrier₁ phase and code phase are trackedindependently but interactively.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda receiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a composite modulation function which is the sum of twodifferent sub-carriers with unequal rates and which rates are differentto the code rate the receiver comprising processing means arranged to:

generate a first estimate of delay based on the code modulation only;

generate a second estimate of delay based on the lower frequencycomponent of the sub-carrier modulation only

generate a third estimate of delay based on the higher frequencycomponent of the sub-carrier modulation only, and

determine a single delay estimate from the first, second and third delayestimates.

The present invention further provides a receiver for receiving anavigation signal comprising a carrier modulated by a code modulationfunction of a given code rate and further modulated by a compositesub-carrier modulation function having first and second components withtwo different rates both of which are different to the code rate, thereceiver comprising processing means arranged to:

-   -   generate a first estimate of delay based on the code modulation;    -   generate a second estimate of delay based on the first component        of the sub-carrier modulation; and    -   generate a third estimate of delay based on the second component        of the sub-carrier modulation; and    -   determine a further delay estimate from the first second and        third delay estimates.        The present invention still further provides a receiver for        receiving a navigation signal comprising a carrier modulated by        a code modulation function of a given code rate and further        modulated by a composite sub-carrier modulation function having        first and second components with two different rates both of        which are different to the code rate, the receiver comprising        processing means arranged to:    -   generate independently first, second and third estimates of        delay based on the code modulation, the first component of the        sub-carrier modulation, and the second component of the        sub-carrier modulation respectively; and    -   determine a further delay estimate from the first second and        third delay estimates.

The essence of some embodiments of the invention is that it estimatesthe signal delay in three independent ways and then combines all threeestimates to arrive at one overall signal delay estimate. If prior artis applied to MBOC the receiver would correlate the modulation in thereceived signal with only a single modulation function, which is thecombination of the code modulation and the composite sub-carriermodulation. Up to now dealing with the correlation function

( ), as in FIG. 6 which results from this action, has been consideredunavoidable, because the combined modulation has been perceived to beintrinsic and inseparable. Some embodiments of the invention contradictthis perception. They recognise that correlating the received signalwith the component sub-carrier modulation function and code modulationfunction can be done separately, so avoiding the need to contemplate theconventional correlation function. They further recognise that the twocomponents in the composite sub-carrier can be tracked separately.

In some embodiments of the invention the delay in the MBOC signal isestimated in three different and independent ways—in a triple estimate.A first non-ambiguous lower accuracy estimate is used to resolve theambiguities in a second higher accuracy estimate. This first estimate isderived only from the phase of the code modulation in the BOC signal; ittreats the BOC modulation as a ‘virtual’PSK and ignores the two subcarrier components. A second estimate is derived only from the phase oflow frequency component sub carrier modulation in the MBOC signal andignores the code and the high frequency component sub carrier. A thirdestimate is derived only from the phase of high frequency component subcarrier modulation in the MBOC signal and ignores both the code and thelower frequency sub-carrier. The code estimate resolves the ambiguity inthe second estimate which in turn resolves the ambiguity in the thirdeven higher accuracy estimate.

A four-loop receiver can be used for the optimal triple estimate of thedelay in a selected MBOC transmission. In some embodiments an innerdelay-locked loop (DLL) tracks the delay as embodied in the code phase;a lower frequency sub-carrier locked loop (SLL₁) independently tracksthe same delay as embodied in the first component sub-carrier phase,while a higher frequency sub-carrier locked loop (SLL₂) independentlytracks the same delay as embodied in the second component sub-carrierphase. Thus three independent delay estimates are calculated. A fourthouter loop may track and lock to the carrier phase and/or frequency ofthe particular satellite signal. All four loops may operatesimultaneously, independently yet co-operatively. This implementationmay be contrasted with a conventional receiver which uses only twoloops, where the single delay estimate is derived from the tracking ofthe correlation function in a delay-locked loop (DLL) while in paralleland simultaneously the carrier phase and/or frequency is tracked by asecond phase locked loop (PLL) or frequency locked loop (FLL).

By virtue of the triple estimate principle in some embodiments of thisinvention the MBOC correlation function

( ) with its secondary and tertiary peaks does not exist and there areno secondary peaks or triple peaks on which a false lock would occur.

In some embodiments of a four-loop receiver the DLL locks to the peak ofthe same Λ( )-shaped function as the standard GPS, so ensuring a smoothand non-ambiguous acquisition of a delay estimate. The SLL₁ howeverlocks to the nearest peak of the continuous first sub-carriercorrelation function—which is a triangular function of periodicity ofthe low frequency sub-carrier component. This loop estimate has higheraccuracy but has an inherent ambiguity in integer multiples of firstsub-carrier half cycles. There is no ‘wrong peak’ in this concepthowever and this ambiguity is acceptable. For, in a further step, theambiguity in this SLL₁ estimate is automatically and instantly resolvedby comparison with the DLL estimate.

The SLL₂ however, in some embodiments, locks to the nearest peak of thecontinuous second sub-carrier correlation function—which is a triangularfunction of periodicity of the high frequency sub-carrier component.This loop estimate has higher accuracy but has an inherent ambiguity ininteger multiples of second sub-carrier half cycles. There is no ‘wrongpeak’ in this concept however and this ambiguity is acceptable. For, ina further step, the ambiguity in this SLL2 estimate is automatically andinstantly resolved by comparison with the corrected SLL1 estimate.

The combination of SLL₂, SLL₁ and DLL estimates can now provide theinherently higher accuracy due to MBOC modulation on the signal(comparing with PSK on the basis of the same chip rate), with theambiguity now resolved.

Because the allocated power to the lower frequency sub-carrier is muchhigher than allocated to the higher frequency sub-carrier an optimallinear combination may be made of the two SLL estimates to generate afourth estimate with even higher accuracy.

Simulations show smooth consistent operation of this joint estimationprocess even in conditions of poor signal to noise.

The four-loop receiver can be implemented with the same variety ofoptions that are available to two loop receivers. The standard option isto track the phase of the carrier—as in so-called ‘coherent DLL’ wherethe outer loop is phase locked to the carrier, using a phasediscriminator. An alternative is to track the frequency of thecarrier—as in so-called ‘incoherent DLL’ where the outer loop isfrequency locked to the carrier, using a frequency discriminator.Various possible phase and frequency discriminators can be used.

Various possible discriminators for the two SLLs can also be used. Avariety of standard discriminators for the DLL loop can also be used. Inparticular the options between coherent early late processing (CELP) andnon-coherent early late processing (NELP) continue to be available notonly to the code discriminator on the DLL, but also for the sub-carriertracking on the SLLs. Known technologies and variants, including methodsfor reducing effect of multipath and currently used in two-loop systemwill transfer to the new four loop system without complication.

In some embodiments the received signal could more than two, for examplethree sub-carrier modulation components, in which case a quadrupleestimate could be made

Preferred embodiments of the invention are now described, by way ofexample only, with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graphical illustration of a PSK modulated signal accordingto the prior art;

FIG. 2 is a graphical illustration of a correlation function for the PSKmodulated signal shown in FIG. 1 according to the prior art;

FIG. 3 is a graphical illustration of a basic sine-BOC modulated signalaccording to the prior art;

FIG. 4 a is a graphical illustration of an ideal correlation functionfor the BOC modulated signal shown in FIG. 3 according to the prior art,showing examples of both correct tracking and false tracking;

FIG. 4 b is a graphical illustration of a correlation function forfiltered and phase distorted correlation function for the BOC example ofFIG. 3, showing deleterious effect on relative amplitudes of primary andnearest secondary peak;

FIG. 5 is a graphical illustration of a basic sine-MBOC modulated signalaccording to the prior art;

FIG. 6 a is a graphical illustration of a correlation function for theMBOC modulated signal shown in FIG. 5 according to the prior art,showing examples of correct tracking;

FIG. 6 b is a graphical illustration of a correlation function for theMBOC modulated signal shown in FIG. 5 according to the prior art,showing examples of false tracking;

FIG. 6 c is a graphical illustration of a correlation function forfiltered and phase distorted correlation function for the MBOC exampleof FIG. 5, showing deleterious effect on relative amplitudes of primaryand nearest secondary peak;

FIG. 7 is a schematic illustration of the overall MBOC receiveraccording to a first preferred embodiment of the invention;

FIG. 8 is a functional expansion of the correlation part 9 of areceiver;

FIG. 9 shows the continuous triangular correlation in either of thesub-carrier component trial delay dimensions only;

FIG. 10 is the nominal correlation in the code delay dimension only;

FIG. 11 is a CELP discriminator function in either of the componentsub-carrier delay dimensions only;

FIG. 12 is a CELP discriminator function in the code delay dimensiononly;

FIGS. 13, 14 and 15 are computer-generated syntheses illustratingoperation of the MBOC receiver; and

FIG. 16 shows an example of the top-level operations and tasks of a GNSSsoftware receiver.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 7, an MBOC receiver 1 according to a first preferredembodiment of the present invention is arranged to receive a MBOCmodulated signal via a right-hand circularly polarised antenna 2. Theantenna 2 feeds the received signal to a pre-amplifier 3, which includesa filter for filtering the received signal, a circuit for blockingstrong interfering signals and a Low Noise Amplifier (LNA) foramplifying the received signal. The LNA effectively sets the receiver'snoise figure, normally around 2 dB, and provides around 30 dB gain. Thepre-amplifier 3 feeds the filtered, amplified signal to a down-converter4 for a first stage down-conversion of the signal to a suitableintermediate frequency (IF). The signal is down-converted in multiplestages and filtered to eliminate unwanted image signals.

The down-converter 4 feeds the down-converted signal to an Analogue toDigital Converter (ADC) 5 for converting the signal to the digitaldomain. The ADC 5 can quantise the signal to one, two or more bits. Inthis embodiment, because the ADC 5 uses multi-bit quantisation, thereceiver 1 incorporates an automatic gain control (AGC) circuit 6 tomaintain proper distribution of the signal across the quantisationlevels. The output of the AGC circuit 6 feeds back to the down-converter4 to enable control of the signal level input to the ADC 5 and hencemaintain proper amplitude distribution of the signal output by the ADC5. The ADC 5 is arranged to output the digital signal u(t) to thetriple-estimator 8. This has a correlator stage 9 and a processing stage10. In this embodiment, the triple estimator 8 is implemented inhardware. So, the correlator stage 9 comprises an Application SpecificIntegrated Circuit/Field Programmable Gate-Array (ASIC/FPGA) and theprocessing stage 10 is a microprocessor. The triple estimator 8estimates the delay τ between transmission and reception of the receivedsignal and outputs the delay estimate via output 11. A clock signal c(t)from reference oscillator at 7 is provided to the down-converter 4, ADC6 and the triple estimator 8.

FIG. 8 shows a detailed functional description to the correlator 9. Theinput signal u(t) splits into an upper in-phase and lower quadrature armand is processed through four stages. The incoming signal is mixed withreplica carrier, sub carrier 2, and sub carrier 1 and code waveforms,each generated by separate digitally controlled oscillators (DCO) 12, 17₂, 17 ₁ 18 respectively. First there is multiplication by a phase orquadrature reference signal from the carrier DCO; then multiplication bya ‘prompt’ linear combination of the two sub-carriers, by early or latereference signal from the sub-carrier DCO₂, by early or late referencesignal from the sub-carrier DCO₁, finally multiplication by a prompt,early or late reference signal from the C/A code generator. Theresulting signal combinations are accumulated over the code period andeight correlation results formed. The extreme right of the diagram showsthe interaction through a data bus to the microprocessor 10.

The input signal u(t) at 5 can be described (neglecting additive noiseand other (M)BOC signals simultaneously present) asu(t)=A×cos(ω₀ t+φ)×(√{square root over (x ₁)}s ₁(t−τ)+√{square root over(x ₂)}s ₂(t−τ))×a(t−τ)×d  (1)where A is amplitude, cos(ω₀t+φ) represents the carrier signal afterdown conversion to an intermediate frequency (IF) ω₀ with phase φ,s₁(t−τ) and s₂(t−τ) are the sub-carrier modulations in the receivedsignal at delay τ, x₁ and x₂ describe the relative apportionment ofpower, a(t−τ) is the code modulation in the received signal at delay τand d is a polarity with dε(−1,+1). Here s₁( ) is the BOC(1,1) componentwhile s₂( ) is the BOC(6,1) component.

The invention depends on the fact that sub-carrier₁ is half-periodicover a relatively short sub-chip width T_(S1), and sub-carrier₂ which ishalf periodic over an even shorter time of a sub-chip width T_(S2) andthat expression (1) is mathematically identical tou(t)=A×cos(ω₀ t+φ)×(√{square root over (x ₁)}s ₁(t−τ* ₁)+√{square rootover (x ₂)}s ₂(t−τ* ₂))×a(t−τ)×d*  (2)where valuesτ*₁ =τ+n ₁ T _(S1)τ*₂ =τ+n ₂ T _(S2)  (3)are multi-valued shifted offset delays depending on an arbitrary integermultiple n₁ of the sub-chip width T_(S1) and integer multiple n₂ of thesub-chip width T_(S2). It is necessary to note a restriction on theintegers. Comparing (1) with (2) it is evident that if n₁ is an oddnumber then n₂ must be an odd number; or if n₁ is an even number then n₂must be an even number, otherwise the correct shape of the compositemodulation is not preserved.

Irrespective of these offset delays it should be understood that theactual sub-carrier delay and the code delay for any actually receivedsignal are still the same as in (1). The receiver must always estimatethis actual non-ambiguous delay τ in the code function a( ). It ishowever only necessary for the same receiver to seek to estimate theambiguous and offsets τ*₁ and τ*₂ in the sub-carrier functions s₁( ) ands₂( ) respectively and still maintain signal to noise optimality. Thisresult is entirely different from present art implementations ofBOC/MBOC where these ambiguities must be prevented, and correlationsneed to be reset if they occur. Therefore the offset delays τ*₁ and τ*₂relative to the true delay τ can be treated as if they were independentquantities as in (2), without regard to (1), and three independentestimates are thereby generated. Only in a final correction stage is itadmitted that all three estimates of the true delay τ are related, andtheir values arithmetically combined according to a vernier principle(see from eqs. 35).

Referring to FIG. 8, the correlator stage 9 of the triple estimator 8receives the digital signal u(t) from the ADC 5 and the clock signalc(t) from the reference oscillator 7. A carrier Digital ControlledOscillator (DCO) 12 of the correlator stage uses the clock signal c(t)to generate In-phase (I) and Quadrature (Q) reference signals r_(I)(t),r_(Q)(t) at the IF ω₀ with trial phase {circumflex over (φ)}, e.g.r ₁(t)=+cos(ω₀ t+{circumflex over (φ)})  (4)andr _(Q)(t)=sin(ω₀ t+{circumflex over (φ)})  (5)

The multiplier 13 then multiplies the digital signal u(t) with referencer_(I)(t) and the I signal filter 14 filters the result to output anin-phase signal v_(I)(t) in the I channel; while the Q signal multiplier15 multiplies the digital signal u(t) with reference r_(Q)(t) and the Qsignal filter 16 filters the result to output quadrature signal v_(Q)(t)in the Q channel. The I and Q signals can be described (neglectingadditive noise and other (M)BOC signals simultaneously present) asv _(I)(t)=cos(φ−{circumflex over (φ)})×(A ₁ ×s ₁(t−τ* ₁)+A ₂ ×s ₂(τ*₂))×a(t−τ)×d  (6)v _(Q)(t)=sin(φ−{circumflex over (φ)})×(A ₁ ×s ₁(t−τ* ₁)+A ₂ ×s ₂(t−τ*₂))×a(t−τ)×d  (7)where identity is made thatA ₁=√{square root over (x ₁)}×AA ₂=√{square root over (x ₂)}×A  (8)To simplify the maths instead of (6) and (7) one can writev _(I)(t)=A×cos(φ−{circumflex over (φ)})×s(t,τ* ₁τ*₂)×a(t−τ)×d  (9)v _(Q)(t)=A×sin(φ−{circumflex over (φ)})×s(t,τ* ₁,τ*₂)×a(t−τ)×d  (10)where the composite modulation is describeds(t,τ* ₁,τ*₂)=√{square root over (x ₁)}s ₁(t−τ*₁)+√{square root over (x₂)}s ₂(t−τ*₂)  (11)

A lower frequency sub-carrier DCO 17 ₁ uses the clock signal c(t) inputat 7 and the sub-carrier modulation function s₁( ) to generate Prompt(P₁), Early (E₁) and Late (L₁) gate sub-carrier reference signalss₁(t−{circumflex over (τ)}*₁), s₁(t−{circumflex over (τ)}*₁+T_(D1)/2),and s₁(t−{circumflex over (τ)}*₁−T_(D1)/2) respectively, where{circumflex over (τ)}*₁ is a trial sub-carrier delay and T_(D1) is thetotal separation between E₁ and L₁ gates. The separation or gate widthT_(D1) can be selected freely in the range T_(S2)≦T_(D1)≦T_(S1).

Similarly a higher frequency sub-carrier DCO 17 ₂ uses the clock signalc(t) and the sub-carrier modulation function s₂( ) to generate Prompt(P₂), Early (E₂) and Late (L₂) gate sub-carrier reference signalss₂(t−{circumflex over (τ)}*₂),s₂(t−{circumflex over (τ)}*₂+T_(D2)/2),and s₂(t−{circumflex over (τ)}*₂−T_(D2)/2) respectively, where{circumflex over (τ)}*₂ is a trial sub-carrier delay and T_(D2) is thetotal separation between E₂ and L₂ gates. The separation or gate widthT_(D2) is conventionally fixed at T_(D2)=T_(S2), although if thetransmitted bandwidth can support it, lower values will give improvedaccuracy.

Similarly, a code DCO 18 uses the clock signal c(t) and the codemodulation function a(t) to generate P, E and L gate code referencesignal a(t−{circumflex over (τ)}), a(t−{circumflex over (τ)}+T_(DC)/2),a(t−{circumflex over (τ)}T_(DC)/2) respectively, where {circumflex over(τ)} is a trial code delay and T_(DC) is the total separation between Eand L gates. The separation T_(DC) can be selected freely in the rangeT_(S1)≦T_(DC)≦T_(C).

The overall correlator stage 8 multiplies the I and Q signals v_(I)(i),v_(Q)(t) by appropriate combinations of the P, E and L gate sub-carrierreference signals s₁(t−τ*₁), s₁(t−{circumflex over (τ)}₁+T_(D1)/2), ands₁(t−{circumflex over (τ)}*₁−T_(D1)/2), the P, E and L gate sub-carrierreference signals s₂(t−τ*₁), s₂(t−{circumflex over (τ)}*₂+T_(D2)/2), ands₂(t−{circumflex over (τ)}*₂−T_(D2)/2) along with the P, E and L gatecode reference signals a(t−{circumflex over (τ)}), a(t−{circumflex over(τ)}+T_(DC)/2), a(t−{circumflex over (τ)}−T_(DC)/2). Eight demodulatedsignals are generated: I channel sum sub carrier P gate code P gatesignal v_(III)(t); I channel sub carrier₁ E₁ gate code P gate signalv_(IE1I)(t); I channel sub carrier₁ L₁ gate code P gate signalv_(IL1I)(t), I channel sub carrier₂ E₂ gate code P gate signalv_(IE2I)(t), I channel sub carrier₂ L₂ gate code P gate signalv_(IL2I)(t); I channel sum sub carrier P gate code E gate signalv_(IIE)(t); I channel sum sub carrier P gate code L gate signalv_(IIL)(t); Q channel sum sub carrier P gate code P gate signalv_(QII)(t). Algebraicallyv _(III)(t)=v _(I)(t)×s(t,{circumflex over (τ)}* ₁,{circumflex over(τ)}*₂)×a(t−{circumflex over (τ)})  (12)v _(IE1I)(t)=v _(I)(t)×s ₁(t−{circumflex over (τ)}* ₁ +T_(D1/2))×a(t−{circumflex over (τ)})  (13)v _(IL1I)(t)=v _(I)(t)×s ₁(t−{circumflex over (τ)}* ₁ +T_(D1/2))×a(t−{circumflex over (τ)})  (14)v _(IE2I)(t)=v _(I)(t)×s ₂(t−{circumflex over (τ)}* ₂ +T_(D2/2))×a(t−{circumflex over (τ)})  (15)v _(IL2I)(t)=v _(I)(t)×s ₂(t−{circumflex over (τ)}* ₂ +T_(D2/2))×a(t−{circumflex over (τ)})  (16)v _(IIE)(t)=v _(I)(t)×s(t,{circumflex over (τ)}* ₁,{circumflex over(τ)}*₂)×a(t−{circumflex over (τ)}+T _(DC/2))  (17)v _(IIL)(t)=v _(I)(t)×s(t,{circumflex over (τ)}* ₁,{circumflex over(τ)}*₂)×a(t−{circumflex over (τ)}−T _(DC/2))  (18)v _(QII)(t)=v _(Q)(t)×s(t,{circumflex over (τ)}* ₁,{circumflex over(τ)}*₂)×a(t−{circumflex over (τ)})  (19)where the composite trial modulation aboves(t,{circumflex over (τ)}* ₁,τ*₂)=√{square root over (x ₁)}s₁(t−{circumflex over (τ)}* ₁)+√{square root over (x ₂)}s ₂(t−{circumflexover (t)}* ₂)  (20)These multiplications are implemented by: first and second multipliers19, 20 multiplying the I signal v_(I)(t) with P gate sum sub-carriers(t,{circumflex over (τ)}*₁,{circumflex over (τ)}*₂) and P gate code tooutput demodulated, signal v_(III)(t); third₁ and fourth₁ multipliers21₁, 22₁ multiplying the I signal v_(I)(t) with E₁ gate sub-carrier andP gate code to output second₁ demodulated signal v_(IE1I)(t); fifth₁ andsixth₁ multipliers 23₁, 24₁ multiplying the I signal v_(I)(t) with L₁gate sub-carrier and P gate code to output third₁ demodulated signalv_(IL1I)(t); third₂ and fourth₂ multipliers 21₂, 22₂ multiplying the Isignal v_(I)(t) with E₂ gate sub-carrier and P gate code to outputsecond_(B) demodulated signal v_(IE2I)(t); fifth₂ and sixth₂ multipliers23₂, 24₂ multiplying the I signal v_(I)(t) with L₂ gate sub-carrier andP gate code to output third_(B) demodulated signal v_(IL2I)(t); firstand seventh multipliers 19, 25 multiplying the I signal v_(I)(t) with Pgate composite sub-carrier and E gate code to output fourth demodulatedsignal v_(IIE)(t); first and eighth multipliers 19, 26 multiplying the Isignal v_(I)(t) with P gate composite sub-carrier and L gate code tooutput fifth demodulated signal v_(IIL)(t); and ninth and tenthmultipliers 27, 28 for multiplying the Q signal v_(Q)(t) with P gatecomposite sub-carrier and P gate code to output sixth demodulated signalv_(QII)(t).

The demodulated signals v_(III)(t), v_(IE1I)(t), v_(IL1I)(t),v_(IE2I)(t), v_(IL2I)(t), v_(IIE)(t), v_(IIL)(t) and v_(QII)(t), arethen integrated by integrators 29 to 34 respectively. The integrators 29to 34 perform the integration over a fixed time, which in thisembodiment is the same as the code period T_(G). In other embodiments,the integration time can be an integer multiple of the code periodT_(G), so that the integration time is typically of the order of a fewmilliseconds in total.

The output of each of the integrators 29 to 34 is sampled by theprocessing stage 10 at the end of each fixed time and the integrators 29to 34 reset to zero. The outputs of the integrators 29 to 34 can bedescribed by a set of eight correlations w_(III)[k], w_(IE1I)[k],w_(IL1I)[k], w_(IE2I)[k], w_(IL2I)[k], w_(IIE)[k], w_(IIL)[k] andw_(QII)[k] for each sample k=1, 2, 3 . . . . The purpose of introducingthis index k is to clarify the nature of a time series beinggenerated—the actual practical software does not need to implement acount notation. The values of these correlations depend of thedifference between the trial phase {circumflex over (φ)} and the truephase φ the difference between the trial sub-carrier delay {circumflexover (τ)}*₁ and the offset sub-carrier delay τ*₁, the difference betweenthe trial sub-carrier delay {circumflex over (τ)}*₂ and the offsetsub-carrier delay τ*₂, and the difference between the trial code delay{circumflex over (τ)} and the true code delay τ. The I sub-carrier Pgate and code P gate correlation w_(III)[k] can be expressed exactlyw _(III) [k]=A×cos(φ−{circumflex over (φ)})×χ({circumflex over(τ)}*₁−{circumflex over (τ)}*₁,{circumflex over (τ)}*₂−{circumflex over(τ)}*₂,{circumflex over (τ)}−τ)×d*  (21)where χ( . . . ) is a three-dimensional correlation function. Thisfunction is not easily displayed. The three-dimensional correlationfunction χ( . . . ) has multiple ‘peaks’ when the trial code delay{circumflex over (τ)} equals the true code delay τ i.e.{circumflex over (τ)}=τ  (22)and the trial sub-carrier delay {circumflex over (τ)}*₁ is equal to anyof the multiple values of the sub-carrier code delay τ₁*, i.e. the truecode delay τ plus a positive or negative integer n multiple of thesub-carrier symbol duration T_(S1) i.e.{circumflex over (τ)}*₁ =τ+n ₁ T _(S1)  (23)while the trial sub-carrier delay {circumflex over (τ)}*₂ is equal toany of the multiple values of the sub-carrier code delay τ*₂, i.e. thetrue code delay τ plus a positive or negative integer n multiple oftwice the sub-carrier symbol duration T_(S2) i.e.{circumflex over (τ)}₂ *=τ+n ₂ T _(S2)  (24)The discriminator action meets the requirement that integer n₂ must beodd if n₁ is odd and even if n₁ is even. In consequence while the{circumflex over (τ)}*₁ estimate can shift by arbitrary integer multipleof T_(S1) the {circumflex over (τ)}*₂ estimate will shift by integermultiples of 2T_(S2).

For explanatory purposes, the I sub-carrier P gate and code P gatecorrelation w_(III)[k] can be approximated by the expressionw _(III) [k]=A×cos(φ−{circumflex over (φ)})×(x ₁ trc ₁(τ−{circumflexover (τ)}*₁)+x ₂ trc ₁(τ−{circumflex over (τ)}₂*))×Λ({circumflex over(τ)}−τ)×d*  (25)where trc₁( ) is a continuous triangular cosine of periodicity 2T_(S1),trc₂( ) is a continuous triangular cosine of periodicity 2T_(S2). FIG. 9sketches the general shape; while Λ( . . . ) is the correlation functionof a PSK modulated signal having the same code rate as the receivedsignal. This is shown in FIG. 10

The other correlations w_(IE1I)[k], w_(IE1I)[k], w_(IE2I)[k],w_(IL2I)[k], w_(IIE)[k], w_(IIL)[k] and w_(QII)[k] are likewisesufficiently well approximated mathematically byw _(IE1I) [k]≈A ₁×cos(φ−{circumflex over (φ)})×trc ₁({circumflex over(τ)}*₁−τ₁ *−T _(D1)/2)×Λ({circumflex over (τ)}−τ)×d*  (26)w _(IL1I) [k]≈A ₁×cos(φ−{circumflex over (φ)})×trc ₁({circumflex over(τ)}*₁−τ₁ *−T _(D1)/2)×Λ({circumflex over (τ)}−τ)×d*  (27)w _(IE2I) [k]≈A ₂×cos(φ−{circumflex over (φ)})×trc ₂({circumflex over(τ)}*₂−τ₂ *−T _(D2)/2)×Λ({circumflex over (τ)}−τ)×d*  (28)w _(IL2I) [k]≈A ₂×cos(φ−{circumflex over (φ)})×trc ₂({circumflex over(τ)}*₂−τ₂ *−T _(D2)/2)×Λ({circumflex over (τ)}−τ)×d*  (29)w _(IIE) [k]≈A×cos(φ−{circumflex over (φ)})××Λ({circumflex over (τ)}−τ−T_(DC)/2)×d*  (30)w _(IIL) [k]≈A×cos(φ−{circumflex over (φ)})×s(τ,{circumflex over(τ)}*₁,{circumflex over (τ)}₂*)×Λ({circumflex over (τ)}−τ+T_(DC)/2)×d*  (31)w _(QII) [k]≈A×sin(φ−{circumflex over (φ)})×s(τ,{circumflex over(τ)}*₁,{circumflex over (τ)}₂*)×Λ({circumflex over (τ)}−τ)×d*  (32)

It can be appreciated that, when the I channel sub carrier₁ E₁ gate codeP gate correlation w_(IE1I)[k] has the same value as the I channelsub-carrier₁ L₁ gate of code P gate the correlation w_(IL1I)[k], i.e.w_(IE1I)[k]=w_(IL1I)[k], this because the E₁ and L₁ gates for thesub-carrier₁ reference signal have the same value.

Similarly, when the I channel sub carrier₂ E₂ gate code P gatecorrelation w_(IE2I)[k] has the same value as the I channel sub carrier₂L₂ gate code P gate correlation w_(IL2I)[k] i.e. w_(IE2I)[k]=w_(IL2I)[k]this is because the E₂ and L₂ gates for the sub-carrier₂ referencesignals have the same value.

Similarly, when the I channel sum sub carrier P gate code E gatecorrelation w_(IIE)[k] has the same value the I channel sum sub carrierP gate code L gate correlation w_(IIL)[k], i.e. w_(IIE)[k]=w_(IIL)[k],this because the E and L gates for the code have the same value.

Similarly when phase lock has been achieved the Q channel correlationw_(QII)[k] is zero, i.e. w_(QII)[k]=0, because the phase estimate{circumflex over (φ)} is the same as the true phase φ plus or minus aninteger number of carrier half cycles, and the sine function inexpression ( ) is zero.

Any difference between the correlation w_(IE1I)[k] and the correlationw_(IL1I)[k] is proportional to the difference between the sub-carriertrial delay {circumflex over (τ)}*₁ and the nearest multi-value of thesub-carrier delay τ*₁. Consequently, the processing stage 10 carries outa subtraction step 35 ₁ that subtracts correlation w_(IE1I)[k] from thecorrelation w_(IL1I)[k] to give a sub-carrier₁ difference correlationw_(IQ1I)[k]. This can be expressed mathematically asw _(IQ1I) [k]≈A ₁×cos(φ−{circumflex over (φ)})×Trs ₁(τ*₁−{circumflexover (τ)}*₁)×trc ₂({circumflex over (τ)}*₂−{circumflex over(τ)}*₂)×Λ({circumflex over (τ)}−τ)×d*  (33-1)where Trs₁( ) is a trapezium sine discriminator function of periodicity2T_(S1) depending on the difference between the trial sub-carrier delay{circumflex over (τ)}*₁ and the multivalued sub-carrier delay τ*₁. FIG.11 shows this general function.

Any difference between the correlation w_(IE2I)[k] and the correlationw_(IL2I)[k] is proportional to the difference between the sub-carriertrial delay {circumflex over (τ)}*₂ and the nearest multi-value of thesub-carrier delay τ*₂.

CELP

According to one embodiment the principle of coherent early-lateprocessing (CELP) may be adopted. Consequently, the processing stage 10carries out a subtraction step 35 ₂ that subtracts correlationw_(IE2I)[k] from the correlation w_(IL2I)[k] to give a sub-carrier₂difference correlation w_(IQ2I)[k]. This can be expressed asw _(IQ2I) [k]≈A ₁×cos(φ−{circumflex over (φ)})×trc ₁({circumflex over(τ)}*₁−{circumflex over (τ)}*₁)×Trs ₂({circumflex over(τ)}*₂−{circumflex over (τ)}*₂)×Λ({circumflex over (τ)}−τ)×d*  (33-2)where Trs₂( ) is a trapezium sine discriminator function of periodicity2T_(S2) depending on the difference between the trial sub-carrier delay{circumflex over (τ)}*₂ and the multivalued sub-carrier delay τ*₂, againas shown in FIG. 11.

Similarly, any difference between the I sub-carrier P gate and I code Egate correlation w_(IIE)[k], and the correlation w_(IIL)[k] isproportional to the difference between the trial code delay {circumflexover (τ)} and the true code delay τ. Consequently, the processing stage10 carries out a subtraction step 36 that subtracts correlationw_(IIE)[k] from the correlation w_(IIL)[k] to give a code differencecorrelation w_(IIQ)[k]. This can then be expressed asw _(IIQ) [k]A×cos(φ−{circumflex over (φ)})×(x ₁ trc ₁(τ−{circumflex over(τ)}*₁)+x ₂ trc ₁(τ−{circumflex over (τ)}*₂))×_(V) ^(Λ)(τ−{circumflexover (τ)})×d*  (34)where V^(Λ)( ) is a discriminator function and is shown in FIG. 12.

Finally, any non-zero value of the Q sub-carrier P gate and Qsub-carrier P gate correlation w_(QII)[k] is approximately proportionalto the difference between the trial phase {circumflex over (φ)} and thetrue phase φ within an arbitrary number of carrier half cycles.

It should be noted that in this account an E gate is subtracted from anL gate in order to ensure correct polarity of loop correction in termsof a code and sub-carrier delay estimate. In an equivalent descriptionan L gate is subtracted from an E gate, in order to ensure correctpolarity of loop correction as expressed in terms of a code andsub-carrier phase estimate. This is because conventionally ‘phase’ and‘delay’ which are equivalent ways of describing shifts in periodicwaveforms are generally perceived as having opposite signs.

Finally, any non-zero value of the Q sub-carrier P gate and Qsub-carrier P gate correlation w_(QII)[k] is approximately proportionalto the difference between the trial phase {circumflex over (φ)} and thetrue phase φ.

NELP

An alternative embodiment according to the principle of non-coherentearly late processing (NELP) may be adopted and is described below in‘alternative embodiments of error discriminators’

From the overall structure of the equations and with the quadruple loopaction ideally in the absence of noise the carrier phase {circumflexover (φ)}→φ+nπ where n is an odd or even integer, while the three timeestimates {circumflex over (τ)}, {circumflex over (τ)}*₁, and{circumflex over (τ)}*₂ converge ideally and independently to the valuesgiven as in (22), (23) and (24) respectively. The {circumflex over (τ)}estimate is any unambiguous estimator of the true delay τ but can beshown to be the least accurate, in the presence of noise. The{circumflex over (τ)}*₁ is more accurate since it exploits thesub-carrier modulation but is offset by an arbitrary integer multiple n₁of sub-chip width T_(S1). A simplest procedure to derive a correctedestimate combines the two

$\begin{matrix}{{\hat{\tau}}_{1}^{+} = {{\hat{\tau}}_{1}^{*} + {{{round}( \frac{\hat{\tau} - {\hat{\tau}}_{1}^{*}}{T_{S\; 1}} )} \times T_{S\; 1}}}} & ( {35\text{-}1} )\end{matrix}$This estimate corrected can then be used to correct the even betterestimate based on the faster sub-carrier component

$\begin{matrix}{{\hat{\tau}}_{2}^{+} = {{\hat{\tau}}_{2}^{*} + {{{round}( \frac{{\hat{\tau}}_{1}^{*} - {\hat{\tau}}_{2}^{*}}{T_{S\; 2}} )} \times T_{S\; 2}}}} & ( {35\text{-}2} )\end{matrix}$finally, and recognising that the MBOC proposal puts considerably lesspower in the higher sub-carrier component, an optimal linear combinationmay be formed{circumflex over (τ)}⁺ =w ₁{circumflex over (τ)}₁ ⁺ +w ₂{circumflex over(τ)}₂ ⁺  (35-3)where coefficient w₁ and w₂ can be established from standard theory ofleast square estimation.Rather than a double rounding procedure the preferred embodiment enablesautomatic integer correction within the loops operation so that{circumflex over (τ)}*₁→{circumflex over (τ)}₁ ⁺ and {circumflex over(τ)}*₂→{circumflex over (τ)}₂ ⁺ and there is no proliferation ofdifferent variable namesCode Processing Description (CELP Implementation)

All processing actions will be described and also summarised in pseudocode. Execution of this block of computer code is synchronised to everycorrelation and is updated here according to a count k.

Correlations w_(III)[k], w_(IQ1I)[k], w_(IQ2I)[k], w_(IIQ)[k] andw_(QII)[k] are input to this processing block. Timing errors e_(τ1*)[k],e_(t2*)[k] and e_(τ)[k] and phase error e_(φ)[k] are generated from thecorrelations in order to steer the trial phase {circumflex over (φ)}[k],trial delays {circumflex over (τ)}*₁[k], {circumflex over (τ)}*₂[k] and{circumflex over (τ)}[k] towards true phase φ and true delays τ*₁, τ*₂and τ respectively. Also responsive DLL gate widths T_(DC)[k] and SLL₁gate width T_(D1)[k] are output—which vary in response to conditions. Anoptimal linear combination {circumflex over (τ)}⁺ of the SLL estimatesis also computed.

The block of computer pseudo-code may be summarised as follows

→ w_(III) w_(IQ1I) w_(IQ2I) w_(IIQ) w_(QII) Δ{circumflex over (τ)}₁Δ{circumflex over (τ)}₂ {circumflex over (τ)}₁* {circumflex over (τ)}₂*{circumflex over (τ)} {circumflex over (φ)} T_(D1) T_(DC) {circumflexover (d)} ← sgn(w_(III)) compute sign 36-1 e_(φ) ← w_(QII) × {circumflexover (d)} PLL error 36-2 e_(τ1)* ← w_(IQ1I) × {circumflex over (d)} SLL₁error 36-3₁ e_(τ2)* ← w_(IQ2I) × {circumflex over (d)} SLL₂ error 36-3₂e_(τ) ← w_(IIQ) × {circumflex over (d)} DLL error 36-4 f_(φ) ← f_(φ) +e_(φ) update phase estimate 36-5 {circumflex over (φ)} ← {circumflexover (φ)} + k₁f_(φ) + k₂e_(φ) {circumflex over (τ)}₂* ← {circumflex over(τ)}₂* + k_(τ2)*e_(τ2)* update SLL₂ estimate 36-6₂ {circumflex over(τ)}₁* ← {circumflex over (τ)}₁* + k_(τ1)*e_(τ1)* update SLL₁ estimate36-6₁ {circumflex over (τ)} ← {circumflex over (τ)} + k_(τ)e_(τ) updateDLL estimate 36-7 {circumflex over (τ)}⁺ ← w₁{circumflex over (τ)}₁* +w₂{circumflex over (τ)}₂* update optimal joint 36-8 estimate If|Δ{circumflex over (τ)}₁| > T_(S1)/2 test tracking of SLL₁ 36-9₁ againstDLL {circumflex over (τ)}₁* ← {circumflex over (τ)}₁* +sign(Δ{circumflex over (τ)}₁) × T_(S1) boot SLL₁ estimate 36-10₁Δ{circumflex over (τ)}₁ ← 0 reset filter₁ output 36-11₁ T_(DC) ← T_(C)raise gate width DLL 36-12₁ otherwise Δ{circumflex over (τ)}₁ ← K_(F) ×({circumflex over (τ)} − {circumflex over (τ)}₁* − Δ{circumflex over(τ)}₁) + Δ{circumflex over (τ)}₁ filter estimate₁ difference 36-13₁T_(DC) ← K_(D) × (T_(S1) − T_(DC)) + T_(DC) relax gate width DLL 36-14₁If |Δ{circumflex over (τ)}2| > T_(S2)/2 test tracking of SLL₂ 36-9₂against SLL₁ {circumflex over (τ)}₂* ← {circumflex over (τ)}₂* +sign(Δ{circumflex over (τ)}₂) × T_(S2) boot SLL₂ estimate 36-10₂Δ{circumflex over (τ)}₂ ← 0 reset filter₂ output 36-11₂ T_(D1) ← T_(S1)raise gate width of SLL₁ 36-12₂ otherwise Δ{circumflex over (τ)}₂ ←K_(F) × ({circumflex over (τ)}₁* − {circumflex over (τ)}₂* −Δ{circumflex over (τ)}₂) + Δ{circumflex over (τ)}₂ filter estimate₂difference 36-13₂ T_(D1) ← K_(D) × (T_(S2) − T_(D1)) + T_(D1) relax gatewidth SLL₁ 36-14₂ ← Δ{circumflex over (τ)}₁ Δ{circumflex over (τ)}₂{circumflex over (τ)}⁺ {circumflex over (τ)}₁* {circumflex over (τ)}₂*{circumflex over (τ)} {circumflex over (φ)} T_(D1) T_(DC)

DETAILED DESCRIPTION

The processing stage 1 is a limiter to estimate the sign of the Isub-carrier P gate and code P gate correlation w_(III)[k] (which may beeither positive or negative). The ‘sgn’ function delivers either +1 or−1 depending on the polarity of the correlation.

Every Ts, notated here as an event by a unit increment in count k, theprocessing stage 10 then computes the three feed-back error signalse_(φ)[k] e_(τ1*)[k] e_(t2*)[k] e_(τ)[k] at 2, 3₁ 3₂, and 4 respectivelyby multiplying the respective Q sub-carrier P gate and Q code P gatecorrelation w_(QII)[k], sub-carrier difference correlations w_(IQ1I)[k]and w_(IQ2I)[k] and code difference correlation w_(IIQ)[k] by the sgn( )signal {circumflex over (d)}[k].

The count notation ‘[k]’ is deliberately omitted since in the actualalgorithm this count need not be recorded.

The processing stage then filters the error signals in order toincrement or decrement the trial phase {circumflex over (φ)},sub-carrier trial delays {circumflex over (τ)}*₁ {circumflex over (τ)}*₂and code trial delay {circumflex over (τ)} as in 5, 6₁, 6₂ and 7respectively.

Of the three timing estimates, {circumflex over (τ)}*₂ with which SLL₂tracks the sub carrier component at f₂=6 MHz is the most accurate butpotentially ambiguous by multiples of T_(S2)=1/12 μs, while {circumflexover (τ)}*₁ with which SLL₁ tracks the sub carrier component at f₂=1 MHzis the less accurate but potentially ambiguous by multiples ofT_(S1)=1/2 μs, and {circumflex over (τ)} with which DLL tracks the codecomponent is the least accurate but quite unambiguous.

But because of the lower power in the MBOC component the difference inaccuracy between the SLL₁ and SLL₂ estimates is not so large.Consequently it is worth while to form an optimal linear mix of the twoestimates, after the values have been corrected, as is shown in line 8to get an estimate which is the best of all.

Again, the count notation ‘[k]’ is deliberately omitted since in theactual algorithm this count need not be recorded.

In this embodiment the carrier phase correction is implemented by asecond order loop, where phase error e_(φ), increments an integratedphase error f_(φ), which direct and integrated errors update a currentphase estimate via two gain constants k₁ and k₂. The SLL time estimatesimplement a first order loops via a gain constants k_(τ1*) and k_(τ2*)respectively and the DLL time estimate implements a first order loop viaa gain constant k_(τ).

With increasing count and in the realistic presence of noise theseerrors go to zero on average i.e. e_(φ)[k]→0, e_(τ)[k]→0 ande_(τ1*)[k]→0 e_(τ2*)[k]→0

The remainder of the processing block is concerned with corrections whenneeded to the potentially ambiguous estimates.

In line 9 ₁ the filtered difference Δ{circumflex over (τ)}₁ between SLL₁estimate {circumflex over (τ)}*₁[k] and the DLL estimate {circumflexover (τ)}[k] was evaluated on previous iteration (previous k value).

If the difference Δ{circumflex over (τ)}₁ is now found to have exceededhalf a sub-chip width T_(S1) then the SLL₁ estimate is deemed to haveslipped. This estimate is therefore booted, i.e. appropriatelyincremented or decremented as in 10 ₁ and the difference Δ{circumflexover (τ)}₁ reset to zero at 11 ₁. Further, the DLL gate width isexpanded from whatever is its current narrower width (T_(DC)) to a fullchip width T_(C) as in 12 ₁. The purpose of this manoeuvre is to speedup acquisition because it is likely that the DLL is in the process ofacquiring lock.

Otherwise it may be that the filtered difference between the twoestimates has not exceeded half a sub-chip width. In which case a firstorder difference filter updates Δ{circumflex over (τ)}₁ using the newlyavailable updates {circumflex over (τ)}*₁ and {circumflex over (τ)} asin 13 ₁. A gain term K_(F) controls the response time of this differencefilter. Further, the code gate width T_(DC) decrements exponentially,and in due course, over sufficient number of iterations this width willsettle asymptotically on a minimum value—made here to be equal to thesub-chip width T_(S1) as in 14 ₁. The settling time of this isdetermined by a controller gain K_(D).

The point of controlling the DLL gate downwards to this minimum is inorder to minimise the noise in the DLL loop, which if excessive couldtrigger a false decision in line 9 ₁. In this way the operating range ofthe receiver is extended downwards to the lowest possible carrier tonoise density ratio C/N₀. for a given loop bandwidth B_(L). In thisembodiment the DLL gate width T_(DC)[k] therefore becomes a dynamicvariable over the range T_(S1)≦T_(DC)≦T_(C).

A similar action takes place with respect to the filtered differenceΔ{circumflex over (τ)}₂. The test for the SLL₂ estimate deemed to haveslipped if it has exceeded a half sub-chip width T_(S2)/2—see line 9 ₂.Alignment of the adjusted estimates preserves the correct shape of themultiplexed subcarriers as in FIG. 5 The reason is that in the Costasloop action respond only to the sign of estimate {circumflex over(d)}[k] as determined by the state of {circumflex over (φ)}[k]{circumflex over (τ)}*₁ and {circumflex over (τ)}. It will not respondto the value of {circumflex over (τ)}*₂ since in the two components ofthe sum modulation s(t,{circumflex over (τ)}*₁, {circumflex over (τ)}*₂)the s₁( ) component is dominating. Consequently, while the timediscriminator characteristic of error e_(τ1*) is periodic over T_(S1)the time discriminator characteristic of error e_(τ2*) is periodic over2T_(S2). In the event of a detected slip the SLL₁ gate width isaugmented, anticipating an acquisition state. If no slip is detectedthis gate width is allowed to relax back to the steady state value.

If the difference Δ{circumflex over (τ)}₂ is now found to have exceededa half sub-chip width T_(S2)/2 as at 9 ₂ then the SLL₂ estimate isdeemed to have slipped. This is therefore booted, i.e. appropriatelyincremented or decremented and the difference Δ{circumflex over (τ)}_(e)is reset to zero in 10 ₂ and 11 ₂. Further, the SLL₁ gate width isexpanded from whatever is its current narrower width (T_(D1)) to a fullsub-chip width T_(S1) in 12 ₂. The purpose of this manoeuvre is to speedup acquisition because it is likely that the SLL₁ is in the process ofacquiring lock.

Otherwise it may be that the filtered difference between the twoestimates has not exceeded a full sub-chip width. In which case a firstorder difference filter updates Δ{circumflex over (τ)}₂ using the newlyavailable updates {circumflex over (τ)}*₁ and {circumflex over (τ)}*₂ asin 13 ₂. A gain term K_(F) controls the response time of this differencefilter. Further, the gate width T_(D1) decrements exponentially, and indue course, over sufficient number of iterations this width will settleasymptotically on a minimum value—made here to be equal to the sub-chipwidth T_(S2). The settling time of this is determined by a controllergain K_(D).

The point of controlling the SLL₁ gate downwards to some minimum is inorder to minimise the noise in the SLL₁ loop, which if excessive couldtrigger a false decision at 9 ₂. In this way the receiver may operate inthe lowest possible carrier to noise density ratio

C/N₀. for a given loop bandwidth B_(L).

In these correction stages it is admitted that the estimates {circumflexover (τ)}*₁[k] {circumflex over (τ)}*₂[k] and {circumflex over (τ)}[k]are necessarily linked, because the difference between them, afterrounding, should be an integer multiple of the sub chip width T_(S1) andan integer multiple of the sub chip width T_(S2), respectively, andassuming that all three loops are locked (converged) and the input C/N₀is sufficiently high. This best combination of the three estimates whichfinally yield an optimal linear combination {circumflex over (τ)}⁺[k] isupdated every correlation interval.

The system as described above with reference to FIGS. 7-12 eliminatesthe possibility of slip or false node tracking in an MBOC receiver whilefully exploiting the potential of MBOC modulation.

As an essential qualification is noted that the system fails if theloops lose lock. But this is true of all loop-based systems. The systemalso fails if the filtered difference of estimates falls randomlyoutside the bounds|Δ{circumflex over (τ)}₁ |>T _(S1)/2  (37)|Δ{circumflex over (τ)}₂ |>T _(S2)/2  (38)which in principle can occur because of excessive noise in the variousestimates, even if the loops are in lock, for too low an input carrierto noise density ratio (CNDR) and/or too high a loop bandwidth B_(L).Theory finds however that this restriction on the allowed range of CNDRand B_(L). is not practically onerous. The value of the DLL gate widthT_(DC), which controls the DLL discriminator action is an automaticcompromise. To maximise speed of acquisition it is switched to thehighest value which is the chip width T_(C) This gives the fastestresponse of the DLL in the initial acquisition. In a detected steadystate the relaxation of T_(DC) down to sub-chip width T_(S1) willhowever minimise the noise in the DLL estimate and extend the basicperformance envelope. Similarly the value of the SLL₁ gate width T_(D1),which controls the SLL₁ discriminator action is an automatic compromise.To maximize speed of acquisition it is switched to the highest valuewhich is the sub-chip width T_(S1). This gives the fastest response ofthe SLL₁ in the initial acquisition. In a detected steady state therelaxation of T_(D1) down to the smaller sub-chip width T_(S2) willhowever minimise the noise in the SLL1 estimate and extend the basicperformance envelope.

The failure condition are however fail safe since the receiver canalways measure for itself when this condition has arisen.

Allowing for Phase Distortion

It was claimed that the prior art receiver designed according to theVEVL, amongst other problems, is vulnerable to phase distortion (seeFIG. 6 c). The same effect manifests itself here as non integer shiftsto the two SLL estimates. Now (2) is literally true and instead of (3)one must writeτ*₁ =τ+n ₁ T _(S1)+ε₁τ*₂ =τ+n ₂ T _(S2)+ε₂  3*where non-integer errors ε₁ and ε₂ are due to group delay distortion.The corresponding modifications needed in the pseudo code can be done ina number of ways. The simplest is to modify 36-8 to{circumflex over (τ)}⁺ ←w ₁×({circumflex over (τ)}*₁−{circumflex over(ε)}₁)+w ₂×({circumflex over (τ)}*₂−{circumflex over (ε)}₁)  36-8*and modify (36-13₁) and (36-13₂) accordingly so thatΔ{circumflex over (τ)}₁ ←K _(F)×({circumflex over (τ)}−{circumflex over(τ)}*₁+{circumflex over (ε)}₁−Δ{circumflex over (τ)}₁)+Δ{circumflex over(τ)}₁  36-13*₁Δ{circumflex over (τ)}₂ ←K _(F)×({circumflex over (τ)}−{circumflex over(ε)}₁−{circumflex over (τ)}*₂+{circumflex over (ε)}₂−Δ{circumflex over(τ)}₂)+Δ{circumflex over (τ)}₂  36-13*₂where corrections {circumflex over (ε)}₁ and {circumflex over (ε)}₂ aresupplied most simply in a preliminary calibration.Practical ImplementationThe correlator architecture of a GNSS BOC receiver requires relativelyfew changes compared to a GNSS PSK receiver in order to implement thetriple estimate in a quadruple loop technique. This process isequivalent in both hardware and software receivers.

FIG. 16 shows an example of the top-level operations and tasks of a GNSSsoftware receiver according to a further embodiment of the invention.The initialisation involves setting up the software and starting thecorrelator channels running. After initialisation the software enablesthe software interrupts. Typically two types of interrupt are used; afast rate (≈1 ms) interrupt for the tracking task which takes thehighest priority and a slower rate (≈100 ms) interrupt for themeasurement task which is given a lower priority. The tracking taskreads the accumulator values, estimates the navigational data state andupdates all four loops with new estimates of carrier₁, sub carrier, subcarrier₂ and code phase. The measurement task provides the detailedmeasurements required to form the navigation solution such as readingthe carrier, the two sub carriers and code DCO values and necessarycounters in the correlator. Under these essential tasks priority can begiven to the various navigational tasks.

Table T1 shows the hardware requirements of each correlator channelbased on receiver architecture designed to operate at an intermediatefrequency IF of 11.38 MHz, with a 50 MHz sampling rate, 100 msmeasurement interval (TIC period) and 2-bit quantisation. The hardwarerequirements of the quadruple loop receiver as detailed in Table 1 areeasily achievable (12 channels or more) with most modern ASIC and FPGAdesigns. Two levels of complexity are distinguished—the minimumcomponents needed for the outer loop embodying a DLL—as given in thedetailed description and FIG. 8 plus the detailed pseudo-code listing ofEqs (36). A further level of complexity requires the additionalcomponents as shown in extreme right columns for the purposes describedin the next section.

TABLE 1 Hardware requirements of triple loop architecture per channel.Number required per channel Components Size basic extended Multipliers 4× 1 14 +14 2 × 2 2 Digitally Controlled 31 bits 4 (Carrier, Oscillators(DCO) (frequency resolution = Sub carrier and 23.03 mHz) Code DCOs)Accumulators 19 bits 8 +14 Counters 21 bits 1 (carrier cycles in 100 ms)20 bits 2 (sub carrier cycles up to 10.23 MHz) 20 bits 1 (code chips upto 10.23 Mcps) 11 bits 1 (epoch counter 1 ms epochs) Registers 31 bits 3(Carrier, (phase register) Sub carrier and Code DCO phase)Extensions and Improvements

In the standard literature numerous improvements and alternatives aredescribed to enable double loop implementation of standard PSK-CDMA.Without exception, after appropriate modification these may be appliedto the quadruple loop receiver of MBOC.

Additional Correlations

Not shown in FIG. 8 are potential improvements and alternatives,obtainable from computing further processing the down converted signals.These by natural extension for n=1 and n=2v _(IEnE)(t)=v _(I)(t)×s _(n)(t−{circumflex over (τ)}*+T_(Dn/2))×a(t−{circumflex over (τ)}+T _(DC/2))  (39)v _(ILnE)(t)=v _(I)(t)×s _(n)(t−{circumflex over (τ)}*−T_(Dn/2))×a(t−{circumflex over (τ)}+T _(DC/2))  (40)v _(IEnL)(t)=v _(I)(t)×s _(n)(t−{circumflex over (τ)}*+T_(Dn/2))×a(t−{circumflex over (τ)}+T _(DC/2))  (41)v _(ILnL)(t)=v _(I)(t)×s _(n)(t−{circumflex over (τ)}*−T_(Dn/2))×a(t−{circumflex over (τ)}+T _(DC/2))  (42)v _(QEnI)(t)=v _(Q)(t)×s _(n)(t−{circumflex over (τ)}*+T_(Dn/2))×a(t−{circumflex over (τ)})  (43)v _(QLnI)(t)=v _(Q)(t)×s _(n)(t−{circumflex over (τ)}*−T_(Dn/2))×a(t−{circumflex over (τ)})  (44)v _(QIE)(t)=v _(Q)(t)×s(t,{circumflex over (τ)}* ₁,{circumflex over(τ)}*₂)×a(t−{circumflex over (τ)}+T _(DC/2))  (45)v _(QIL)(t)=v _(Q)(t)×s(t,{circumflex over (τ)}* ₁,{circumflex over(τ)}*₂)×a(t−{circumflex over (τ)}+T _(DC/2))  (46)where again the composite trial modulation aboves(t,{circumflex over (τ)}* ₁,τ*₂)=√{square root over (x ₁)}s₁(t−{circumflex over (τ)}* ₁)+√{square root over (x ₂)}s ₂(t−{circumflexover (τ)}* ₂)  (11)

From these may be integrated to corresponding correlations every Tseconds to w_(IEnE)[k], w_(ILnE)[k], w_(IEnL)[k], w_(ILnL)[k],w_(QEnI)[k], w_(QLnI)[k], w_(QIE)[k], w_(QIL)[k] respectively. Further,there may be extracted correlation differencesw _(IQnQ)=(w _(ILnL) −w _(IEnL))−(w _(ILnE) −w _(IEnE))  (47)w _(QQnI) =w _(QLnI) −w _(QEnI)  (48)w _(QIQ) =w _(QIL) −w _(QIE)  (49)

These correlations may be used to enhance and generalise operation ofthe invention in many different ways.

Improvement from Carrier Aiding

The invention admits the standard technique of carrier aiding—thetechnique of importing into the delay estimate a correction proportionalto the Doppler frequency. The equations (36-6) can be modifiedaccordingly to read{circumflex over (τ)}*₂←{circumflex over (τ)}*₂ +k _(φ2*) f _(φ) +k_(τ2*) e _(τ2*)  (50){circumflex over (τ)}*₁←{circumflex over (τ)}*₁ +k _(φ1*) f _(φ) +k_(τ1*) e _(τ1*)  (51){circumflex over (τ)}←{circumflex over (τ)}+k _(φ) f _(φ) +k _(τ) e_(τ)  (52)

Term f_(φ) is the same as in the PLL equations (36-5) and is interpretedas a scaled Doppler shift estimate (either positive or negativedepending on the sign of the relative motion). Constants k_(φ), k_(φ2*)and k_(φ1*) are pre-calculated to provide the necessary open loopcorrection of Doppler shift appropriately scaled down to the code rateand sub-carrier rate respectively.

Alternative Embodiments of Error Discriminators

The computation to error sequences according to (36-2), (36-3), and(36-4) utilised only one of many possible discriminators. The standardalternatives available in the dual-loop single-estimate conventional PSKreceivers may be adopted here, after appropriate modification, and inparticular non-coherent early late processors (NELP).PLL DiscriminatorsFrom (36-1) and (36-2) the equivalent formulation ise _(φ) ←w _(QII) [k]×sgn(w _(III))  (53)Dispensing with sgn( ) operation givese _(φ) ←w _(QII) [k]×w _(III)  (54)Expressing this as a ratio gives

$\begin{matrix} e_{\phi}arrow\frac{w_{QII}}{w_{III}}  & (55)\end{matrix}$To improve tracking when SLL is not yet in lock one can adopte _(φ) ←w _(QII) ×sgn(w _(III))+w _(QQI) ×sgn(w _(IQI))  (56)from which removing sgn( ) givese _(φ) ←w _(QII) ×w _(III) +w _(QQI) ×w _(IQI)  (57)SLL_(n) DiscriminatorsFrom (36-1) and (36-3) the equivalent formulation ise _(τn*) ←w _(IQnI) ×sgn(w _(III))  (58)Dispensing with the sgn( ) operation givese _(τn*) ←w _(IQnI) ×w _(III)  (59)Expressing this as a ratio gives

$\begin{matrix} e_{\tau\; n^{*}}arrow\frac{w_{IQnI}}{w_{III}}  & (60)\end{matrix}$DLL DiscriminatorFrom (36-1) and (36-4) the equivalent formulation ise _(τ) ←w _(IIQ) ×sgn(w _(III))  (61)Removing the sgn( ) operation givese _(τ) ←w _(IIQ) ×w _(III)  (62)Incoherent DLL Embodiment

It has been claimed that an ‘incoherent DLL’ receiver is more effectivethan ‘coherent DLL’. A representative paper is “Theory and Performanceof narrow correlation spacing in a GPS receiver”, A. J. Van Dierendoncket al ION National Technical Meeting San Diego Calif. January 1992. Thisconcept requires a frequency locked loop (FLL) instead of a PLL in theouter loop. This type of system is readily incorporated into the tripleestimate concept for MBOC-GNSS requiring however some of the additionalcorrelations identified from (39) to (46).

The implementation of an FLL requires only that the difference betweenthe phase and the phase estimateΔφ=φ−{circumflex over (φ)}  (63)be made to settle at some arbitrary constant rather than zero. The aimhowever with the control of the time estimates in the two loops is againthat {circumflex over (τ)}*₁→τ+n₁T_(S1), {circumflex over(τ)}*₂→T+n₂T_(s2) and {circumflex over (τ)}→τ. But effective tracking ofthe SLL₁ sub carrier phase and SLL₂ (to yield estimates {circumflex over(τ)}*₁ and {circumflex over (τ)}*₂ respectively) and the DLL (to yieldestimate {circumflex over (τ)}) must generate an error signal which isindifferent to an arbitrary constant offset between {circumflex over(φ)} and φ.

It is necessary then to realise a frequency discriminator from thecorrelations and/or correlation differences, and to ensure that theSLL₁,SLL₂ and DLL discriminators are indifferent to carrier phase error.

FLL Discriminators

First we can compute a frequency error from current and previouscorrelations and correlation differencese _(ωQI) ←w _(QII) sgn(w _(III) ⁻)−w _(III) sgn(w _(QII) ⁻)  (64)where the notation w_(III) ⁻ and w_(QII) ⁻ stands for correlation in theprevious correlation (earlier by T) One can also forme _(ωII) ←w _(III) sgn(w _(III) ⁻)+w _(QII) sgn(w _(QII) ⁻)  (65)which allows a 2-quadrant computation

$\begin{matrix}{e_{\omega} = {\frac{\langle e_{\omega\;{QI}} \rangle}{\langle e_{\omega\;{II}} \rangle} \approx {\tan({\Delta\omega})}}} & (66)\end{matrix}$Alternatively a 4 quadrant computatione _(ω)=arctan 2

e _(ωQI)

e _(ωII)

  (67)Another alternative is to dispense with sgn functions as in (64) so thate _(ωQI) ←w _(QII) w _(III) ⁻ −w _(III) w _(QII) ⁻  (68)and one can also forme _(ωII) ←w _(III) w _(III) ⁻ +w _(QII) w _(QII) ⁻  (69)which again allows a 2-quadrant computation or a 4 quadrant comparison.SLL Discriminators (NELP)

The discriminator must work for an arbitrary phase difference ΔφDiscriminator (36-3) does not work in this case, so we need to extend toe _(τn*) ←w _(IQnI) sgn(w _(III))+w _(QQnI) sgn(w _(QII))  (70)One can dispense with sgn( ) to obtaine _(τn*) ←w _(IQnI) w _(III) +w _(QQnI) w _(QII)  (71)DLL Discriminator (NELP)

The discriminator must work for an arbitrary phase difference ΔφDiscriminator (36-4) does not work in this case, so we need to extend toe _(τ) ←w _(IIQ) sgn(w _(III))+w _(QIQ) sgn(w _(QII))  (72)One can dispense with sgn( ) to obtaine _(τ) ←w _(IIQ) w _(III) +w _(QIQ) w _(QII)  (73)Computing the difference of power direct from early and latecorrelations givese _(τ) ←w _(IIL) ² +w _(QIL) ² −w _(IIE) ² −w _(QIE) ²  (74)which one may enhance with further correlations to obtaine _(τ)←(w _(IIL) ² +w _(QIL) ² +w _(IQL) ² +w _(QQL) ²)−(w _(IIE) ² +w_(QIE) ² +w _(IQE) ² +w _(QQE) ²)  (75)Computing the difference of amplitude direct from early and latecorrelations givese _(τ)←√{square root over (w _(IIL) ² −w _(QIL) ²)}−√{square root over(w _(IIE) ² +w _(QIE) ²)}  (76)and computing the normalised difference gives

$\begin{matrix} e_{\tau}arrow\frac{\sqrt{w_{IIL}^{2} - w_{QIL}^{2}} - \sqrt{w_{IIE}^{2} + w_{QIE}^{2}}}{\sqrt{w_{IIL}^{2} - w_{QIL}^{2}} - \sqrt{w_{IIE}^{2} + w_{QIE}^{2}}}  & (77)\end{matrix}$Loop OperationsAn appropriate modification for ‘incoherent DLL’ can be expressed inpseudo code as:ê _(φ) ←ê _(φ) +e _(ωI){circumflex over (f)} _(φ) ←{circumflex over (f)} _(φ) +ê _(φ) FLL  (78{circumflex over (φ)}←{circumflex over (φ)}+k ₁ {circumflex over (f)}_(φ) +k ₂ ê _(φ){circumflex over (τ)}*₁←{circumflex over (τ)}*₁ +k _(τ1*) e _(τ1*) SLL₁  (79){circumflex over (τ)}*₂←{circumflex over (τ)}*₂ +k _(τ2*) e _(τ2*) SLL₂  (80){circumflex over (τ)}←{circumflex over (τ)}+k _(τ) e _(τ) DLL  (81)which can be extended by carrier aiding.Computer Generated Simulation

FIGS. 13, 14 and 15 show a simulation of the quadruple loop-dualestimator in action according to the embodiment of FIG. 8, and asdescribed earlier, according to the CELP principle. The chosenparameters are exactly the same in the two FIGS. 13 and 14 but withoutand with additive noise respectively. The aim here is not only todemonstrate the anti-slip fail safe nature of the quadruple loop butalso to show a typical acquisition process. There is assumed to havebeen an initial search—just as in standard PSK-CDMA—which brings thecode delay estimate within ±T_(C) of the actual input delay andtherefore within range of the DLL discriminator.

Simulation values are deliberately chosen for the most stringent test ofpossible operation. The C/N₀±250 Hz is equivalent to 24 dBHz and is thevery low value chosen in the already cited paper by Fine and Wilson.This carrier to noise density ratio is significantly lower than usualtest conditions for GNSS signals. The MBOC modulation is the oneactually proposed where the high rate component BOC(6,1) is 2/11 of thelow rate component BOC(1,1). This composite modulation confined to thepilot channel which is 50% of the whole power. Correlation interval T=20ms gives 10 dB signal to I channel noise ratio Normalised chip widthT_(C)=1. Normalised sub-chip width T_(S1)=1/2. Normalised sub-chip widthT_(S2)=1/12. The loop bandwidth of B_(L)=2 Hz which is close to thehighest allowed for this low value of C/N₀. The test here shows that thealgorithm will simultaneously acquire all three estimates andinstantaneously correct the SLL₁ estimate from the DLL estimate and theSLL₂ estimate from the SLL₁ estimate, even during the dynamic processwhen the loops are locking up. Tracking performance depends on thedifference between the actual code delay and the initial setting of theloop estimates after an initial search. The example has a synthesisedactual delay τ=τ₀=9.5/12 which is bad start up condition with the DLLand SLL loops originally initialised in this example with {circumflexover (τ)}*₁=0, {circumflex over (τ)}*₂=0 and {circumflex over (τ)}=0,because the initial search result is presumed to be a poor one. Filtergains K_(F)=0.5 and K_(D)=0.02 were chosen empirically as a result ofthese tests.

The rising dotted curve in the upper graph is the DLL estimate.Acquisition by the DLL responds immediately but the other loops hardlymove until count 21 (420 msec); then SLL₁ is booted into action andimmediately after SLL₂. The long dashed curve for SLL₁ shows that itrequires only two steps to get to the final estimate; while thecontinuous curve for SLL₂ shows the expected smaller increments.

The whole point and purpose of the invention is demonstrated here:namely when the loops are active (and the signal to noise is highenough) it is impossible for the higher-accuracy SLL₂ estimate to slipmore than ±T_(S2)/2 out of alignment with the lower accuracy SLL₁estimate which in turn cannot slip more than ±T_(S1)/2 with respect tothe lowest accuracy DLL estimate. Acquisition is complete on a step ataround 50 counts or 1 s. The simulation also monitors the tracking ofthe third carrier tracking loop which here is a 2^(nd) order PLL. Aninput true carrier phase of φ=30 deg was adopted arbitrarily for thisexample. The continuous track on the lower graph of FIG. 13 is the phaseestimate and shows the characteristic overshoot of a under-damped secondorder loop. The dotted and dashed curves on the lower graph show thedynamic response of the gate widths T_(DC) and T_(D1)—opening out whenthere is a perceived need for rapid acquisition and then settling downto lower levels T_(S1) and T_(S2) respectively in due time.

Similar results with additive electrical noise actually present areshown in example from FIG. 14. The acquisition time is accordingly arandom variable. It can take longer; or it can be shorter. Thequasi-random nature of the acquisition process is evident. Yet there isa definite acquisition.

FIG. 15 shows the relative noise levels in steady measurements. Thewidely fluctuating dotted curve is the DLL estimate. The broken curve isthe SLL₁ estimate. The continuous curve is the joint optimal linearestimate computed as described. The much lower timing error in theoptimal estimate is evident.

The advantage of some embodiments of the present invention over theprior art may include the following: the method can realise thepotential accuracy of MBOC Discounting loop settling time (common to allsystems) the correct estimate is essentially instantaneous. The presentinvention avoids locking on a wrong peak (false node), provideduncritical requirements on input carrier to noise density ratio and loopbandwidth are met, since there is no multi-peaked one-dimensionalcorrelation function in the first place. More specifically, while theDLL estimate {circumflex over (τ)} must converge on the true delay, thetwo SLL estimates {circumflex over (τ)}*₁ and {circumflex over (τ)}*₂may converge on arbitrary offsets from this true delay and onlyinstantaneous arithmetic corrections according to Eqs. 35 need beimplemented, without loss of optimality. Equivalently the morecomplicated routines of Esq. 36 allows for arithmetic correctionswithout need for re-setting the corresponding correlations. The receiveris therefore fail safe, in the sense that after loop convergence thehighest quality estimate is immediately and continuously availablethereafter. This is a unique feature to the present invention It is alsoinsensitive to non-linear amplitude/frequency conversion that may bepresent in the transmission chain.

The described embodiments of the invention are only examples of how theinvention may be implemented. Modifications, variations and changes tothe described embodiments will occur to those having appropriate skillsand knowledge. These modifications, variations and changes may be madewithout departure from the scope of the invention defined in the claimsand its equivalents.

The invention claimed is:
 1. A receiver for receiving a navigationsignal comprising a carrier modulated by a code modulation function of agiven code rate and further modulated by a composite sub-carriermodulation function having first and second components with twodifferent rates both of which are different to the code rate, thereceiver comprising a processor arranged to: generate a first estimateof delay based on the code modulation only; generate a second estimateof delay based on the first component of the sub-carrier modulationonly; and generate a third estimate of delay based on the secondcomponent of the sub-carrier modulation only; and determine a furtherdelay estimate from the first, second and third delay estimates; andwherein the rate of the second component is higher than the rate of thefirst component and the processor is arranged in determining the furtherdelay estimate, to recalculate the second estimate by an integer numberof half cycles at the lower sub-carrier frequency to bring it towardsthe first estimate, and to recalculate the third estimate by an integernumber of half cycles at the higher sub-carrier frequency to bring ittowards the second estimate.
 2. A receiver according to claim 1 whereinthe processor is arranged to make a correction to at least one of thesecond and third estimates of delay to correct for phase distortion. 3.A receiver according to claim 2 wherein the correction is a non-integermultiple of the sub-chip width.
 4. A receiver according to claim 1wherein a control means is arranged to determine a combined estimate ofdelay from the third delay estimate and the further delay estimate.
 5. Areceiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a composite sub-carrier modulation function having firstand second components with two different rates both of which aredifferent to the code rate, the receiver comprising a processor arrangedto: generate a first estimate of delay based on the code modulationonly; generate a second estimate of delay based on the first componentof the sub-carrier modulation only; and generate a third estimate ofdelay based on the second component of the sub-carrier modulation only;and determine a further delay estimate from the first, second and thirddelay estimates; and wherein the processor is arranged in determiningthe further delay estimate, to calculate a first delay difference as thedifference between the first and second estimates rounded to an integernumber of first sub-carrier half cycles, and a second delay differenceas the difference between the second and third estimates rounded to aninteger number of second sub-carrier half cycles.
 6. A receiveraccording to claim 5 wherein the processor is arranged, in determiningthe further delay estimate, to add the first delay difference to thesecond estimate of delay and the second delay difference to the thirdestimate.
 7. A receiver for receiving a navigation signal comprising acarrier modulated by a code modulation function of a given code rate andfurther modulated by a composite sub-carrier modulation function havingfirst and second components with two different rates both of which aredifferent to the code rate, the receiver comprising a processor arrangedto: generate a first estimate of delay based on the code modulation onlygenerate a second estimate of delay based on the first component of thesub-carrier modulation only; and generate a third estimate of delaybased on the second component of the sub-carrier modulation only; anddetermine a further delay estimate from the first, second and thirddelay estimates; and wherein the processor is arranged to update thefirst and second estimates iteratively and to calculate the first delaydifference and add it to the second estimate repeatedly; and to updatethe second and third estimates iteratively and to calculate the seconddelay difference and add it to the third estimate repeatedly.
 8. Areceiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a composite sub-carrier modulation function having firstand second components with two different rates both of which aredifferent to the code rate, the receiver comprising a processor arrangedto: generate a first estimate of delay based on the code modulationonly; generate a second estimate of delay based on the first componentof the sub-carrier modulation only; and generate a third estimate ofdelay based on the second component of the sub-carrier modulation only;and determine a further delay estimate from the first, second and thirddelay estimates; and wherein the processor is arranged to update thefirst and second estimates iteratively until they converge towardsrespective final values, to update the second and third estimatesiteratively until they converge towards respective final values, and tocalculate the further delay estimate from the final values.
 9. Areceiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a composite sub-carrier modulation function having firstand second components with two different rates both of which aredifferent to the code rate, the receiver comprising a processor arrangedto: generate a first estimate of delay based on the code modulationonly; generate a second estimate of delay based on the first componentof the sub-carrier modulation only; and generate a third estimate ofdelay based on the second component of the sub-carrier modulation only;and determine a further delay estimate from the first, second and thirddelay estimates; wherein the processor includes: a reference code signalgenerator arranged to generate at least one reference code signal usingthe first estimate of delay; a reference lower frequency sub-carriersignal generator arranged to generate at least one lower frequencyreference sub-carrier signal using the second estimate of delay; and areference higher frequency sub-carrier signal generator arranged togenerate at least one higher frequency reference sub-carrier signalusing the third estimate of delay; and a correlation generator arrangedto generate correlations based on the reference signals and at least onecomponent of the received signal; wherein the at least one lowerfrequency reference sub-carrier signal includes an early reference lowerfrequency sub-carrier signal and a late reference lower frequencysub-carrier signal separated by a gate width time difference; and atleast one higher frequency reference sub-carrier signal includes anearly reference higher frequency sub-carrier signal and a late referencehigher frequency sub-carrier signal separated by a gate width timedifference wherein the gate width time differences are variable; theprocessor being arranged to vary the gate width time difference as thetrial sub-carrier delay is updated; wherein the processor is arranged indetermining the further delay estimate, to calculate a first delaydifference as the difference between the first and second estimatesrounded to an integer number of first sub-carrier half cycles, and asecond delay difference as the difference between the second and thirdestimates rounded to an integer number of second sub-carrier halfcycles, and the processor is arranged to detect a slip condition in theupdating of one of the trial sub-carrier delays corresponding to achange in the estimated value of the associated integral number, and toincrease the gate width time difference in response to the slipcondition.
 10. A receiver according to claim 9 wherein the processor isarranged to use the correlations to generate error estimations for thedelay estimates, and to update the delay estimates based on the errorestimations.
 11. A receiver according to claim 9 wherein the at leastone reference code signal includes an early reference code signal and alate reference code signal separated by a gate width time difference.12. A receiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a composite sub-carrier modulation function having firstand second components with two different rates both of which aredifferent to the code rate, the receiver comprising a processor arrangedto: generate a first estimate of delay based on the code modulationonly; generate a second estimate of delay based on the first componentof the sub-carrier modulation only; and generate a third estimate ofdelay based on the second component of the sub-carrier modulation only;and determine a further delay estimate from the first, second and thirddelay estimates; wherein the processor includes: a reference code signalgenerator arranged to generate at least one reference code signal usingthe first estimate of delay; a reference lower frequency sub-carriersignal generator arranged to generate at least one lower frequencyreference sub-carrier signal using the second estimate of delay; and areference higher frequency sub-carrier signal generator arranged togenerate at least one higher frequency reference sub-carrier signalusing the third estimate of delay; and a correlation generator arrangedto generate correlations based on the reference signals and at least onecomponent of the received signal; and wherein the correlation means isarranged to generate a plurality of correlations that vary in differentways as the trial delay approaches an actual delay and to combine themto determine the error estimation.
 13. A receiver according to claim 12wherein the processor is arranged to combine the correlations in amanner which varies as the delay approaches the actual delay todetermine the error estimations.